1. Field of the Invention
Methods and apparatuses consistent with the present invention relate to time synchronizing based on a time stamp in a packet switching network, and an aspect of the invention relates to a time synchronizing method and apparatus based on a time stamp by which a delta time value and an offset value are calculated and filtered through a loop filter based on the time stamp received from a master node to a slave node to adjust a local clock time based on the delta time value and the offset value so as to synchronize a local clock of the slave node with a local clock of the master node.
2. Description of the Related Art
In general, a master node transmits a time sync message through a forwarding link in a packet switching network to provide a standard time for which all slave nodes refer to the time sync message. The time sync message includes a time stamp through which the slave nodes accurately discern when the master node transmits the time sync message. There are first and second ways of transmitting timings using such time stamps.
In the first way, one node transmits a time stamp to all nodes including slave nodes connected thereto except a master node thereof. Here, the time stamp includes a local clock value read when the time stamp is transmitted. Also, downstream clocks may synchronize with a clock of the master node but may vary due to propagation delays of the downstream clocks.
In the second way, one slave node transmits a time stamp to a master node thereof. The master node recognizes a time when the master node receives the time stamp to transmit to the slave node a response time stamp including a time when the slave node transmits the time stamp, a time when the master node receives the time stamp, and a time when the master node transmits the response time stamp. The slave node may recognize from the response time stamp with the three times a time when the slave node receives the response time stamp and synchronize with the master node, and a propagation delay may be removed due to this synchronization.
The first and second ways do not specify how the time stamps have to be used. Typically, one slave node uses time stamp information to perform an immediate phase adjustment or adjust a local clock rate. In many cases, it is a digital control oscillator (DCO) that is adjusted, i.e., the local free-running clock is used to synthesize a clock whose frequency is adjusted based on the input time stamp value. Also, the first and second ways do not specify whether time stamps are based on the free-running local clock values or the corrected values based on corrections due to previous time stamps. If the time stamps are based on the free-running local clock values, it is required that additional information containing the accumulated time stamp values from all clocks between the slave node and the master node be transmitted. If the time stamps are based on corrected clock values due to previous time stamps, the time stamps are inherently based on accumulated information. However, in the latter the case must be considered where a mode adjusts its local clock value, based on time stamp exchange with its master node, between its receipt of a time stamp from a slave and the sending of a reception of the response to the slave node.
In cases where an immediate phase adjustment is made when a time stamp is received in a slave node, the resulting timing signal contains a phase step at each adjustment. A size of the phase step depends on the clock accuracy and the frequency at which the time stamp is transmitted.
If the clock frequency tolerance is ±y (where y is a pure fraction), and the time between successive time stamps is T, then the maximum phase step is of order 2yT. For example, if y is 100 ppm and T is 10 ms, the maximum phase is 2000 ns; this is excessively large for some applications, e.g., digital video and audio transport in Residential Ethernet (i.e., Audio/Video Bridging Network). This phase step occurs in the synchronization of one slave node to its master node; this phase error will accumulate over a chain of nodes as timing is transferred and the total phase error accumulation will be somewhat larger than 2yT.
In cases where time stamps are used to adjust DCOs that are part of digital phase-locked loops (DPLLs), phase errors can accumulate as timing is transferred over a chain of nodes. The phase accumulation can be controlled by limiting the bandwidths of the DPLLs, gain peaking, and the generation of noise.
For a DCO with given inherent noise level, a narrower bandwidth will result in larger DPLL noise generation. It is also known that after traversing a number of phase-locked loops (PLLs), a phase error increases dramatically; the number of PLLs after which this happens depends on the gain peaking and is smaller for larger gain peaking.
However, use of DPLL structures with smaller gain peaking results in a more sluggish DPLL and the need for a more stable, i.e., lower noise, oscillator. Accordingly, a conventional time synchronizing method is based on larger jitter and wander accumulation or acceptable jitter and wander accumulation but possibly at the cost of a lower noise and therefore more expensive oscillator.